227,67 €
284,59 €
Digital Logic Design Using Verilog
227,67 € 
- Išsiųsime per 10–14 d.d.
Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.
227.67
2025-06-29 23:59:00
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- Autorius: Vaibbhav Taraate
- Leidėjas: Springer
- ISBN-10: 9811632014
- ISBN-13: 9789811632013
- Formatas: 15.6 x 23.4 x 3.2 cm, minkšti viršeliai
- Kalba: Anglų
- Extra -20 % nuolaida šiai knygai su kodu ENG20
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Aprašymas
Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.EXTRA 20 % nuolaida
227,67 €
284,59 €
Išsiųsime per 10–14 d.d.
Kupono kodas: ENG20
Akcija baigiasi už 3d.07:37:44
Nuolaidos kodas galioja perkant nuo 10 €. Nuolaidos nesumuojamos.
- Autorius: Vaibbhav Taraate
- Leidėjas: Springer
- ISBN-10: 9811632014
- ISBN-13: 9789811632013
- Formatas: 15.6 x 23.4 x 3.2 cm, minkšti viršeliai
- Kalba: Anglų
Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.
Atsiliepimai