227,89 €
Decimation Lowpass Filters for Sigma-Delta Modulators
Decimation Lowpass Filters for Sigma-Delta Modulators
227,89 €
  • Išsiųsime per 14–16 d.d.
Inhaltsangabe: Abstract: The purpose of this thesis is to compare several filter topologies used for the decimation of sigma-delta modulated digital signals. The goal is to present optimized filter architectures with regard to an efficient VLSI implementation. A fifth-order 1-bit sigma-delta modulator using local feedback techniques will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 32. The decimation filter must guarantee a…
227.89
  • Autorius: Rüdiger Kusch
  • Leidėjas:
  • Metai: 2002
  • Puslapiai: 188
  • ISBN-10: 3838662326
  • ISBN-13: 9783838662329
  • Formatas: 14.8 x 21 x 1.1 cm, minkšti viršeliai
  • Kalba: Anglų

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Inhaltsangabe: Abstract: The purpose of this thesis is to compare several filter topologies used for the decimation of sigma-delta modulated digital signals. The goal is to present optimized filter architectures with regard to an efficient VLSI implementation. A fifth-order 1-bit sigma-delta modulator using local feedback techniques will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 32. The decimation filter must guarantee a narrow transition band between 0.5 and 0.55 and stopband attenuation of 100dB. Chapter 1 provides a brief introduction into the principles of digital signal processing. The considerations are focused on FIR filters due to the requirements for acoustic applications. Chapter 2 illustrates the proposed overall structure and the design flow. The objective of chapter 3 is to present the principles of oversampling data converters using sigma-delta techniques. The 5V fifth-order SD-modulator with 90dB dynamic range (SNR+THD) will be presented, which has been fabricated in 1.2µm CMOS technology. For the sake of simplicity and robustness, a 1-bit quantizer will be used. Chapter 4 deals with typical hardware realizations of digital filters. Apart from the "brute force" implementation of the multirate filter with identical filters running in parallel, also the LUT-based approach for small filter orders will be presented. Due to the advantages of compact implementation, the bit-serial approach and the bit-serial multiplier are investigated in detail. In chapter 5 the straightforward one-stage multirate FIR filter will be introduced. To satisfy the specifications, a 4096 tap lowpass FIR filter will be designed. The influence of coefficient quantization is investigated and furthermore the "block scaling" method, to represent small values, is presented. The single-stage implementation becomes the more unattractive the higher the filter specifications are. Chapter 6, therefore, focuses
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Inhaltsangabe: Abstract: The purpose of this thesis is to compare several filter topologies used for the decimation of sigma-delta modulated digital signals. The goal is to present optimized filter architectures with regard to an efficient VLSI implementation. A fifth-order 1-bit sigma-delta modulator using local feedback techniques will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 32. The decimation filter must guarantee a narrow transition band between 0.5 and 0.55 and stopband attenuation of 100dB. Chapter 1 provides a brief introduction into the principles of digital signal processing. The considerations are focused on FIR filters due to the requirements for acoustic applications. Chapter 2 illustrates the proposed overall structure and the design flow. The objective of chapter 3 is to present the principles of oversampling data converters using sigma-delta techniques. The 5V fifth-order SD-modulator with 90dB dynamic range (SNR+THD) will be presented, which has been fabricated in 1.2µm CMOS technology. For the sake of simplicity and robustness, a 1-bit quantizer will be used. Chapter 4 deals with typical hardware realizations of digital filters. Apart from the "brute force" implementation of the multirate filter with identical filters running in parallel, also the LUT-based approach for small filter orders will be presented. Due to the advantages of compact implementation, the bit-serial approach and the bit-serial multiplier are investigated in detail. In chapter 5 the straightforward one-stage multirate FIR filter will be introduced. To satisfy the specifications, a 4096 tap lowpass FIR filter will be designed. The influence of coefficient quantization is investigated and furthermore the "block scaling" method, to represent small values, is presented. The single-stage implementation becomes the more unattractive the higher the filter specifications are. Chapter 6, therefore, focuses

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