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- Autorius: Petro Lutsyk
- Leidėjas: Springer
- ISBN-10: 3030432424
- ISBN-13: 9783030432423
- Formatas: 15.6 x 23.4 x 3.3 cm, minkšti viršeliai
- Kalba: Anglų
- Extra -15 % nuolaida šiai knygai su kodu: ENG15
A Pipelined Multi-Core Machine with Operating System Support + nemokamas atvežimas! | knygos.lt
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Aprašymas
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
- MIPS instruction set architecture (ISA) for application and for system programming
- cache coherent memory system
- store buffers in front of the data caches
- interrupts and exceptions
- memory management units (MMUs)- pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
- I/O-interrupt controller and a disk
EXTRA 15 % nuolaida su kodu: ENG15
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- Autorius: Petro Lutsyk
- Leidėjas: Springer
- ISBN-10: 3030432424
- ISBN-13: 9783030432423
- Formatas: 15.6 x 23.4 x 3.3 cm, minkšti viršeliai
- Kalba: Anglų
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
- MIPS instruction set architecture (ISA) for application and for system programming
- cache coherent memory system
- store buffers in front of the data caches
- interrupts and exceptions
- memory management units (MMUs)- pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
- I/O-interrupt controller and a disk
Atsiliepimai