VHDL '92 (el. knyga) (skaityta knyga) | Jean-Michel Berge | knygos.lt

Aprašymas

Introduction: 1. Designer's Concerns. 2. Spirit of VHDL'92. New Simulation Mechanisms: 3. Last-Delta Activation. 4. Shared (Global) Variables. New Structuring Mechanisms: 5. Direct Instantiation. 6. Incremental Binding. 7. Groups. New Interfacing Mechanisms: 8. Foreign Interfaces. 9. Reading and Writing Files. 10. Impure Functions. New Predefined Operators, Functions & Attributes: 11. Shift. 12. XNOR. 13. Predefined Attribute `Driving_Value'. 14. Predefined Attribute `Ascending'. 15. Predefined Attributes 'Behavior' & `Structure'. 16. Predefined Attributes `Image' & `Value'. 17. Attributes `Path_Name'`Instance_Name' `Simple_Name'. Slight Enhancements: 18. Inertial Signal Assignment. 19. Declarative Part in Generate Statements. 20. Mapping Expressions to Input Ports. 21. The New Character Set. 22. Identifier Generalization. 23. Alias Generalization. 24. Access to Predefined Operators. 25. Extension of Bit String Literals. Language Simplifications: 26. Concurrent Signal Assignment. 27. Report Statement. 28. Concatenation Operator. 29. Bracketing. Clarification: 30. Static Expressions. 31. Run-Time Checks. 32. Interface List. 33. Association List. 34. Resolved Subelements in Composites. 35. Labels & User-Defined Attributes. 36. Miscellaneous. Annex: 37. List of Reserved Words. 38. Informal Glossary. 39. Index. List of Figures.